Fault-Secure Parity Prediction Arithmetic Operators

units (adders, ALUs, multipliers, dividers) are essential to fault-tolerant computer designs. Some researchers based early design schemes for such units on arithmetic residue codes.1 Others proposed parity prediction schemes for the same purpose.2 These schemes compute the output operand’s parity as a function of the operator’s internal carries and of the input operands’ parities. The basic drawback of parity prediction is that it may not achieve fault secureness, because single faults propagate on output errors of random multiplicity, which can escape detection by parity code. Arithmetic codes are efficient for checking arithmetic units because these codes survive under most arithmetic operations. Thus, we can implement a self-checking arithmetic operator by using a conventional arithmetic operator for processing the operands’ information parts and a modulo A arithmetic operator for their check parts. (A represents the base of the residue code.) The hardware processing the check parts is constant irrespective of the arithmetic operator’s length, resulting in low area overhead for large operands. Arithmetic codes can ensure fault secureness for most arithmetic operators.3,4 But arithmetic code checking has some drawbacks. First, arithmetic code checkers are complex circuits. Moreover, logic operations and shift operations do not preserve arithmetic codes. Therefore, using such codes in ALUs and shifters requires the implementation of complex circuits for code prediction. In data path buses and registers and in memory systems, we can achieve error detection by using parity code. But arithmetic codes are not compatible with parity checking. Thus, if we use arithmetic code checking for arithmetic operators, we must implement the whole system with arithmetic codes. This is an undesirable solution, especially for large blocks such as RAM systems. Our other choice is to use input and output code translators, which incur area overhead and a performance penalty. For adders and ALUs, a parity prediction scheme has the advantage regardless of operand size. For multipliers the situation is different. The extra area needed for parity prediction is proportional to the size of the arithmetic operator (or to the square of its operands’ size). The extra area for arithmetic coding includes a part proportional to the size of the operands (arithmetic code checker and code translators), plus a constant-size part (the circuit processing the check parts). Thus, for large arrays the area overhead for an arithmetic coding scheme can be significantly lower than for a parity prediction scheme. However, for smalland medium-size operands, parity prediction carries a lower overhead. In addition, parity prediction schemes for ripple-carry adders and multiply and divide arrays involve a lower performance penalty than arithmetic codFault-Secure Parity Prediction Arithmetic Operators PARITY PREDICTION